The position is an exciting opportunity to be part of a dynamic team in the growing markets of secure microcontrollers used in state-of-the-art secure applications including IOT, Mobile, Banking and Brand Protection. The role works within the physical digital team in Singapore that includes all disciplines required for physical design & verification.
Responsibilities:

Work on Synthesis, develop timing constraints
Place and Route, floor planning, power planning, MMMC scenarios, clock tree synthesis, timing, and routing convergence
Static Timing and Crosstalk Analysis, ensure timing closure of full design
Power analysis (IR drop/EM)
Formal verification
Physical verification (LVS/DRC/ERC)
Low Power Implementation
ECO implementation
Schedule preparation and execution adhere to plan.
Good reporting to the management.

Requirements:

Bachelor’s/ Master’s in Electronics Engineering with at least 10 years’ experience in physical design and verification.
Familiar with hierarchical physical design strategies, methodologies, and deep sub-micron technology.
Experience in physical design, mainly floor planning and partitioning, congestion analysis, placement optimization, clock-tree synthesis, and timing closure.
Proficient in static timing analysis.
Proficient in programming/scripting with good coding experience in Tcl/Perl/Python.
Good communication and written skills in English.
Able to work in a multi-cultural team.
Strong analytical and problem-solving skills
Hands-on experience with leading EDA tools (such as Synopsys IC Compiler, Primetime, and Cadence Innovus) in physical implementation flow is mandatory
Good knowledge on EM/IR-Drop/crosstalk analysis (Redhawk), formal or physical verification will be an advantage.

Senior or Staff Back-End IC Design Engineer