Senior SoC Verification Engineer

Overview

Our client is seeking a Senior SoC Verification Engineer to join the global SoC Design Engineering team. This position is responsible for the full verification lifecycle, from system-level concept to post-silicon validation. The ideal candidate will lead the planning, development, and execution of advanced verification methodologies to ensure high-quality silicon designs, while contributing to automation and efficiency improvements across the verification process.

Challenges you would face

Own the complete verification lifecycle from concept through post-silicon support
Develop and execute pre-silicon test plans for digital power IPs
Design and implement testbenches using SystemVerilog UVM methodologies
Create functional coverage and assertion models to validate design integrity
Deploy and optimize UPF power-aware verification flows
Develop automation scripts to enhance verification efficiency
Collaborate with design teams to review functionality and identify potential failure points
Define verification methodologies and determine appropriate environments and tools
Plan test sequences, evaluate results, and implement process improvements
Contribute to post-silicon validation, quality control, and documentation

The ideal candidate

Bachelor’s degree in Electrical Engineering, Computer Science, or related field
7+ years of ASIC design or verification experience, with at least 5 years using UVM and assertion-based verification
Strong hands-on experience with SystemVerilog, VHDL, Verilog, and C/C++
Experience verifying complex SoC systems or subsystems
Proficiency with memory verification VIPs and firmware/driver development
Proven track record across multiple successful tape-outs, from concept to production
Strong analytical and troubleshooting skills with attention to detail
Excellent written and verbal communication skills for cross-functional collaboration

Plus

Experience with formal verification (property checking)
Knowledge of automated testing and electrical testing systems
Familiarity with quality control and design process standards
Experience developing or improving automation tools for verification
Exposure to power-aware design and verification methodologies