Title: Shared Cache Verification Engineer

Contract Role - 100% Remote

Seeking an experienced verification engineer to develop and execute test plans for shared L2 cache coherency in multi-core SoC designs. Responsibilities include building UVM testbenches, creating portable stimulus scenarios for MOESI protocols, integrating snoop controls and CCI interfaces, running simulations/emulation, debugging coherency bugs, and achieving high coverage on intra/inter-cluster traffic.

Key Requirements:

10+ years in ASIC/SoC verification, with expertise in cache coherency (MOESI/MESI), ARM/RISC-V architectures.
Proficiency in SystemVerilog, UVM, assertions, formal methods, and tools like Breker Trek or Synopsys VCS.
Strong knowledge of AXI-ACE, ECC, low-power states, and multi-threaded stress testing.
Experience with many-core designs (16+ cores) and silicon validation a plus.